Yudong Kim

High-k gate stacks for planar, scaled CMOS integrated circuits

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moores Law towards the 10-nm physical gate length regime.

Correcting effective mobility measurements for the presence of significant gate leakage current

A physically based correction for the impact of gate leakage current on the extraction of the effective mobility in MOSFETs has been derived that allows accurate determination of the mobility even when the gate leakage becomes significant. Experimentally, this correction has been applied to MOSFETs with both thin silicon dioxide and high-k gate dielectric, and the efficacy of the correction has been demonstrated for gate leakage up to 10 A/cm/sup 2/.

Resonant optical nonlinearity measurement of Yb(3+) / Al(3+) codoped optical fibers by use of a long-period fiber grating pair.

A new method of measuring optical nonlinearity for resonant nonlinear optical fibers is proposed. A long-period fiber grating (LPG) pair was used to measure the nonlinear refractive index n(2) of a Yb(3+)/Al (3+) codoped optical fiber, which was spliced between the two LPGs, as the fiber was pumped with a laser diode. The nonlinear refractive index of the Yb(3+)/Al (3+) codoped fiber near 1580 nm depended on the pump power. As the pump power increased, the nonlinear refractive index decreased. At launched pump powers of 2-8 mW, the nonlinear refractive index of the Yb(3+)/Al (3+) codoped fiber near 1580 nm was ~7.5x10(-15)m (2)/W .

Fabrication of high quality ultra-thin HfO/sub 2/ gate dielectric MOSFETs using deuterium anneal

The effects of high-temperature deuterium annealing on MOSFETs with HfO/sub 2/ gate dielectric and TaN gate electrode has been studied and compared to the control and forming gas (FG) annealed samples. Both FG and D/sub 2/ anneal improved interface qualities and resulted in better MOSFET characteristics in comparison to control samples. These improvements resulted from both the additional thermal budget of high temperature anneal and the improvement of interface quality caused by the hydrogen and deuterium atoms. But unlike FG D/sub 2/ anneal showed negligible degradation of reliability.

Subnanometer Scaling of HfO2/Metal Electrode Gate Stacks

The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, (i) reduction of the bottom interfacial layer (BIL) using NH 3 interface engineering, (ii) thickness reduction of the HfO 2 dielectric, and (iii) use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the NH 3 BIL with scaled HfO 2 /metal gates and 0.81 nm EOT using the O 3 BIL with scaled HfO 2 /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed.

Conventional poly-Si gate MOS-transistors with a novel, ultra-thin Hf-oxide layer

Conventional poly-Si gate MOS transistors with a high-k gate-dielectric were fabricated using a novel, ultra-thin Hf-oxide. Various integration effects on the high-k layer were studied such as Si-surface preparation, deposition conditions, and post-deposition anneals, demonstrating EOT of 1.6 to 1.2 nm and excellent gate leakage current. Promising transistor behaviors were obtained including electron mobility up to 90% of SiO/sub 2/ at both peak and high-field.

Integration of high-k gate stack systems into planar CMOS process flows

We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.

The effects of nitrogen and silicon profile on high-k MOSFET performance and Bias Temperature Instability

Nitrogen profile has been modulated by inserting Si layer into HfO/sub x/N/sub y/. In this paper, the effects of nitrogen and silicon on MOSFET performance and BTI (Bias Temperature Instability) characteristics have been investigated. Nitrogen incorporation enhanced V/sub TH/ shift for both PBTI (Positive Bias Temperature Instability) and NBTI (Negative Bias Temperature Instability). However, BTI degradation is significantly suppressed by the Si insertion. This improvement can be attributed to the reduction of oxide bulk trapped as well as interface trapped charge generation resulting from the insertion of Si layer.

Integration issues of high-k gate stack: Process-induced charging

Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO/sub 2/, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.

Effects of thin SiN interface layer on transient I-V characteristics and stress induced degradation of high-k dielectrics

In this work, we present the effects of a SiN interface on charge trapping and de-trapping characteristics and time-dependent threshold voltage instability. The use of SiN interface structure was found to reduce the degradation in D/sub it/ and G/sub m/ even though it yielded higher bulk charge trapping. The higher bulk trap was evidenced from larger after-stress V/sub th/ degradation. Thus, it is believed that mobility degradation in HfO/sub 2/ is primarily caused by the degraded quality of the interfacial layer.