Jim Gutt

High-k gate stacks for planar, scaled CMOS integrated circuits

The gate stack should be regarded as a multi-element interfacial layered structure wherein the high-k gate dielectric and gate electrodes (and their corresponding interfaces) must be successfully comprehended. The surface clean and subsequent surface conditioning prior to high-k deposition as well as post-deposition annealing parameters significantly impact the equivalent oxide thickness and leakage current as well as the traditional parameters such as threshold voltage, saturation current, transconductance, and sub-threshold swing. The control of both the fixed electrical charges and charge traps incorporated at the various interfaces and within the high-k bulk film is of paramount importance to achieve the requisite transistor characteristics and, in particular, the effective carrier mobility. Interactive effects within the gate stack process modules and the subsequent integrated circuit fabrication process require the utmost attention to achieve the desired IC performance characteristics and help facilitate the continuance of Moores Law towards the 10-nm physical gate length regime.

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

Experimental study of etched back thermal oxide for optimization of the Si/high-k interface

We have demonstrated a uniform, robust interface for high-k deposition with significant improvements in device electrical performance compared to conventional surface preparation techniques. The interface was a thin thermal oxide that was grown and then etched back in a controlled manner to the desired thickness. Utilizing this approach, an equivalent oxide thickness (EOT) as low as 0.87 nm has been demonstrated on high-k gate stacks having improved electrical characteristics as compared to more conventionally prepared starting surfaces.

Subnanometer Scaling of HfO2/Metal Electrode Gate Stacks

The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, (i) reduction of the bottom interfacial layer (BIL) using NH 3 interface engineering, (ii) thickness reduction of the HfO 2 dielectric, and (iii) use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the NH 3 BIL with scaled HfO 2 /metal gates and 0.81 nm EOT using the O 3 BIL with scaled HfO 2 /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed.

Integration issues of high-k gate stack: Process-induced charging

Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO/sub 2/, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.

Dominant SILC mechanisms in HfO/sub 2//TiN gate nMOS and pMOS transistors

To introduce high-k dielectrics into conventional CMOS product flow, reliability issues of high-k gate stacks need to be addressed. Although several studies have focused on this issue, the physical mechanism of stress-induced degradation in high-k dielectrics is still not clear. In SiO/sub 2//poly-Si gate stacks, most intrinsic degradations are attributed to trap generation leading to the percolation model type failure, while pre-existing defects are believed to contribute to extrinsic mode failure (Olivio, P. et al., 1988). For the HfO/sub 2//TiN gate stack, it has been reported that a similar mechanism was at work (Crupi, F. et al., 2004). However, considering the high density of pre-existing electron traps (Zhan, N. et al., 2003) and the time dependent reversible threshold voltage shift (Lee, B.H. et al., 2004), one may expect that the electron accumulation in the dielectric during electrical stress may cause the modulation of the energy barrier and affect the electron tunneling, which, in turn, may lead to variation of SILC with the stress time. We have investigate the SILC characteristics of HfO/sub 2//TiN gate nMOS and pMOS transistors in conjunction with the trapping/detrapping processes in the high-k dielectric.

EOT scaling and device issues for high-k gate dielectrics

In this paper, we fabricate a high-k transistor for equivalent oxide thickness (EOT) scaling involving ALD and MOCVD.