Jay Rascoe

Schottky Barrier Diodes for Millimeter Wave SiGe BiCMOS Applications

For the first time, a high performance, low leakage Schottky barrier diode (SBD) with cutoff frequency above 1.0 THz in a 130nm SiGe BiCMOS technology for millimeter-wave application is described. Device optimization has been evaluated by varying critical process and layout parameters such as, anode size, cathode depth, cathode resistivity, junction tailoring, and guardring optimization is investigated

CMOS millimeter wave phase shifter based on tunable transmission lines

This paper presents a tunable transmission line (t-line) structure, featuring independent control of line inductance and capacitance. The t-line provides variable delay while maintaining relatively constant characteristic impedance using direct digital control through FET switches. As an application of this original structure, a 60 GHz RF-phase shifter for phased-array applications is implemented in a 32 nm SOI process attaining state-of-the-art performance. Measured data from two phase shifter variants at 60 GHz showed phase changes of 175° and 185°, S21 losses of 3.5-7.1 dB and 6.1-7.6 dB, RMS phase errors of 2° and 3.2°, and areas of 0.073 mm2 and 0.099 mm2 respectively.

High performance, low complexity 0.18 /spl mu/m SiGe BiCMOS technology for wireless circuit applications

High frequency performance at low current density and low wafer cost is essential for low power wireless BiCMOS technologies. We have developed a low-complexity, ASIC-compatible, 0.18 /spl mu/m SiGe BiCMOS technology for wireless applications that offers 3 different breakdown voltage NPNs; with the high performance device achieving F/sub t//F/sub max/ of 60/85 GHz with a 3.0 V BV/sub CEO/. In addition, a full suite of high performance passive devices complement the state-of-the-art SiGe wireless HBTs.

A low complexity 0.13 /spl mu/ SiGe BiCMOS technology for wireless and mixed signal applications

We present IBMs next-generation, cost-performance-optimized BiCMOS technology (BiCMOS 8WL) which combines a state-of-the-art suite of SiGe NPNs, foundry compatible 0.13 μm CMOS, and a rich set of modular passive devices. Intended for a wide variety of supply voltages, the technology, features three different performance NPNs and standard, dual oxide, zero V t , and junction isolated FETs. Optimized for wireless and mixed signal applications, BiCMOS 8WL will enable system on a chip integration for 3G cellular applications.

On-Chip Millimeter-Wave Library Device - Scalable Wilkinson Power Divier/Combiner

On-chip millimeter wave Wilkinson power divider has been developed with the back end of line (BEOL) wiring and enabled as a library device in a 0.13 mum BiCMOS process design kit. The device layout and model are fully scalable, i.e. users can design a power divider at different frequencies or in different reference characteristic impedance systems by inputting the dimensions. Excellent model and hardware correlation has been observed up to 110 GHz. The measured results show that very good performance on-chip Wilkinson power dividers have been obtained in this technology, such as less than about 0.1 dB amplitude imbalance, about 0.8 dB of insertion loss with bandwidth of about 15% of the design frequency (defined at 15 dB return loss level) and about 20 dB of isolations. In addition, the device is the design rule check (DRC) clean and the layout versus schematic (LVS) enabled, which help to shorten the design cycle.

Silicon-chip single and coupled coplanar transmission line measurements and model verification up to 50GHz

Silicon technology on-chip single and coupled coplanar transmission lines have been measured on wafer up to 50 GHz. De-embedding was performed using various methods including the L-2L technique [1,2] by measuring two transmission lines of original and double length. A novel approach has been used for the measurement of the coupled structures using conventional two port VNA. Results are investigated both in S-parameter format and in gamma-Zo format, and compared with EM solver and the parametric IBM coplanar T-line device models discussed elsewhere [3,4] which are available in IBM CMOS and SiGe technology design kits. A comparison with RC model shows the limits of RC model validity, in frequency domain.

Wideband millimeter wave pin diode spdt switch using ibm 0.13µm sige technology

Feasibility of wideband on-chip RF switch operating at millimeter wave frequencies using PIN diodes in IBM .13 mum SiGe technology is demonstrated. A SPDT reflective switch targeting 60 GHz wireless and radar applications is designed, fabricated, and measured. Good correlations between simulation and hardware are reported. Measured data show 2.0 to 2.7 dB of insertion loss over 51 to 78 GHz bandwidth with better than 12 dB return loss and 25 to 35 dB of isolation.

Collector optimization in advanced SiGe HBT technologies

With the advancement of the fT/fMAX performance scaling of SiGe HBTs the breakdown voltage (BVCBO/BVCEO) reduces commensurately, causing design related concerns. It is important, therefore, that multiple fT/BVCEO devices be offered in the RF technologies to meet the varying needs of the communication products. Unlike the GaAs technologies, the SiGe BiCMOS technologies are capable of integrating various flavors of fT/BVCEO SiGe HBT devices at a technology node. In this work, we investigate the tradeoff in fT-BVCEO for advanced SiGe HBTs by various collector optimization schemes such as, subcollector dopant species and concentration, epilayer thickness, SIC and other layout techniques.

A cost-competitive high performance Junction-FET (JFET) in CMOS process for RF & analog applications

in this paper, we present a cost-effective JFET integrated in 0.18µm RFCMOS process. The design is highly compatible with standard CMOS process, therefore can be easily scaled and implemented in advanced technology nodes. The design impact on Ron and Voff is further discussed, providing the insights and guidelines for JFET optimization. Besides the superior flicker noise (1/f noise) characteristics, this JFET device also demonstrates promising RF characteristics such as maximum frequency, linearity, power handling capability, power-added efficiency, indicating a good candidate for RF designs.

On-chip CMOS coplanar transmission line measurements and model verification up to 50 GHz

The results show good agreement between de-embedded measurement and T- line coplanar model in both S-parameters and in Zo representation. In all cases the results of the T-line coplanar model are very close to the corresponding results of the EM solver. The RC model deviates significantly in the frequency domain from the T-line coplanar model results - both in S- parameters and in -Zo representation. The design impact of these deviations depends on the design niche (eg. digital vs. RF), and for a given design niche it may apply only to a given subset of critical wires (eg. clock line, high speed signal line etc.). The criticality of a given wire depends also on the wire length, and the on-chip effective bandwidth (rise time in digital or frequency in RF). For digital designs, the criteria for using a model that includes inductive effects (instead of RC model) was given and discussed previously.The considerations of designing the RF launching structures have been discussed. We have found that a robust optimal design of the RF launching structure allows for the usage of very simple de-embedding techniques up to relatively high frequencies.