Shinichi Takagi

On the universality of inversion layer mobility in Si MOSFET's: Part I-effects of substrate impurity concentration

This paper reports the studies of the inversion layer mobility in n- and p-channel Si MOSFETs with a wide range of substrate impurity concentrations (10/sup 15/ to 10/sup 18/ cm/sup -3/). The validity and limitations of the universal relationship between the inversion layer mobility and the effective normal field (E/sub eff/) are examined. It is found that the universality of both the electron and hole mobilities does hold up to 10/sup 18/ cm/sup -3/. The E/sub eff/ dependences of the universal curves are observed to differ between electrons and holes, particularly at lower temperatures. This result means a different influence of surface roughness scattering on the electron and hole transports. On substrates with higher impurity concentrations, the electron and hole mobilities significantly deviate from the universal curves at lower surface carrier concentrations because of Coulomb scattering by the substrate impurity. Also, the deviation caused by the charged centers at the Si/SiO/sub 2/ interface is observed in the mobility of MOSFETs degraded by Fowler-Nordheim electron injection. >

Comparative study of phonon‐limited mobility of two‐dimensional electrons in strained and unstrained Si metal–oxide–semiconductor field‐effect transistors

The phonon‐limited mobility of strained Si metal–oxide–semiconductor field‐effect transistors (MOSFETs) fabricated on a SiGe substrate is investigated through theoretical calculations including two‐dimensional quantization, and compared with the mobility of conventional (unstrained) Si MOSFETs. In order to match both the mobility of unstrained Si MOSFETs and the mobility enhancement in strained Si MOSFETs, it is necessary to increase the coupling of electrons in the two‐dimensional gas with intervalley phonons, compared to the values used in conventional models. The mobility enhancement associated with strain in Si is attributed to the following two factors: the suppression of intervalley phonon scattering due to the strain‐induced band splitting, and the decrease in the occupancy of the fourfold valleys which exhibit a lower mobility due to the stronger interaction with intervalley phonons. While the decrease in the averaged conductivity mass, caused by the decrease in the occupancy of the fourfold valle...

Fabrication of strained Si on an ultrathin SiGe-on-insulator virtual substrate with a high-Ge fraction

A promising fabrication method for a Si1−xGex-on-insulator (SGOI) virtual substrate and evaluation of strain in the Si layer on this SGOI substrate are presented. A 9-nm-thick SGOI layer with x=0.56 was formed by dry oxidation after epitaxial growth of Si0.92Ge0.08 on a silicon-on-insulator substrate. During the oxidation, Ge atoms were rejected from the surface oxide layer and condensed in the remaining SGOI layer, which was partially relaxed without introducing a significant amount of dislocations. It is found from the analysis of the Raman spectra that the strained Si layer grown on the SGOI layer involves a tensile strain of 1%. This strained Si on the SGOI structure is applicable to sub-100-nm metal–oxide–semiconductor field-effect transistors.

Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

An effective way to reduce supply voltage and resulting power consumption without losing the circuit performance of CMOS is to use CMOS structures using high carrier mobility/velocity. In this paper, our recent approaches in realizing these carrier-transport-enhanced CMOS will be reviewed. First, the basic concept on the choice of channels for increasing on current of MOSFETs, the effective-mass engineering, is introduced from the viewpoint of both carrier velocity and surface carrier concentration under a given gate voltage. Based on this understanding, critical issues, fabrication techniques, and the device performance of MOSFETs using three types of channel materials, Si (SiGe) with uniaxial strain, Ge-on-insulator (GOI), and III-V semiconductors, are presented. As for the strained devices, the importance of uniaxial strain, as well as the combination with multigate structures, is addressed. A novel subband engineering for electrons on (110) surfaces is also introduced. As for GOI MOSFETs, the versatility of the Ge condensation technique for fabricating a variety of Ge-based devices is emphasized. In addition, as for III-V semiconductor MOSFETs, advantages and disadvantages on low effective mass are examined through simple theoretical calculations.

Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology

We have newly developed strained-Si MOSFETs on a SiGe-on-insulator (strained-SOI) structure fabricated by separation-by-implanted-oxygen (SIMOX) technology. Their electron and hole mobility characteristics have been experimentally studied and compared to those of control SOI MOSFETs. Using an epitaxial regrowth technique of a strained-Si film on a relaxed-Si/sub 0.9/Ge/sub 0.1/ layer and the conventional SIMOX process, strained-Si (20 nm thickness) layer on fully relaxed-SiGe (340 nm thickness)-on-buried oxide (100 nm thickness) was formed, and n-and p-channel strained-Si MOSFETs were successfully fabricated. For the first time, the good FET characteristics were obtained in both n-and p-strained-SOI devices. It was found that both electron and hole mobilities in strained-SOI MOSFETs were enhanced, compared to those of control SOI MOSFETs and the universal mobility in Si inversion layer.

Evidence of low interface trap density in GeO2∕Ge metal-oxide-semiconductor structures fabricated by thermal oxidation

We have fabricated GeO2∕Ge metal-oxide-semiconductor (MOS) structures by direct thermal oxidation of Ge substrates. The interface trap density (Dit) of Al∕GeO2∕Ge MOS structures, measured by the low temperature conductance method including the effect of the surface potential fluctuation, is found to be reduced as the oxidation temperature increases. The minimum values of Dit can be obtained for the oxidation around 575°C, which is in the maximum temperature range where GeO volatilization does not occur under atmospheric pressure of O2. It is also found that the hydrogen annealing before Al gate formation is effective for the passivation of GeO2∕Ge interface states. It is clarified, as a result, that the minimum Dit value lower than 1011cm−2eV−1 can be obtained for GeO2∕Ge MOS interfaces fabricated by direct oxidation of Ge substrates.

Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique

A strained Ge-on-insulator (GOI) structure with a 7-nm-thick Ge layer was fabricated for applications to high-speed transistors. The GOI layer was formed by thermal oxidation of a strained SiGe layer grown epitaxially on a silicon-on-insulator (SOI) wafer. In transmission electron microscopy measurements, the obtained GOI layer exhibited a single-crystal structure with the identical orientation to an original SOI substrate and a smooth Ge/SiO2 interface. The rms of the surface roughness of the GOI layer was evaluated to be 0.4 nm by atomic force microscopy. The residual Si fraction in the GOI layer was estimated to be lower than the detection limit of Raman spectroscopy of 0.5% and also than the electron energy loss spectroscope measurements of 3%. It was found that the obtained GOI layer was compressively strained with a strain of 1.1%, which was estimated by the Raman spectroscopy. Judging from the observed crystal quality and the strain value, this technique is promising for fabrication of high-mobilit...

On the universality of inversion layer mobility in Si MOSFET's: Part II-effects of surface orientation

For part I see ibid., vol.41, no.12, pp.2357-62 (1994). This paper reports the studies of the inversion layer mobilities in n-channel MOSFETs fabricated on Si wafers with three surface orientations ([100], [110], and [111]) from the viewpoint of the universal relationship against the effective field, E/sub eff/(=q(N/sub dpl/+/spl eta//spl middot/N/sub s/)//spl epsi/Si). It is found that the universality does hold for the electron mobilities on [110] and [111], when the value of /spl eta/ is taken to be 1/3, different from the electron mobility on [100], where /spl eta/ is 1/2. Also, the E/sub eff/ dependence of the electron mobility is found to differ among [100], [110], and [111] surfaces. This is attributed to the differences in the E/sub eff/ dependence of the mobility limited by surface roughness scattering among the orientations. The origins of E/sub eff/ and /spl eta/ are discussed on the basis of the relaxation time approximation for a 2DEG (2-dimensional electron gas). While the surface orientation dependence of /spl eta/ in phonon scattering can be understood in terms of the subband occupation, it is found that the theoretical formulation of surface roughness scattering, used currently, needs to be refined in order to explain the differences in E/sub eff/ dependence and the value of /spl eta/ among the three orientations. >

Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm

The electrical characteristics of ultrathin-body SOI CMOSFETs with SOI thickness ranging from 2.3 nm to 8 nm are intensively investigated. As a result, it is demonstrated, for the first time, that electron mobility increases as SOI thickness decreases, when SO, thickness is in the range from 3.5 nm to 4.5 nm. In addition, it is demonstrated that, when SOI thickness is thinner than 4 nm, slight (even atomic-level) SOI thickness fluctuations have a significant impact on threshold voltage, gate-channel capacitance, and carrier mobility of ultrathin-body CMOSFETs.

Bending experiment on pentacene field-effect transistors on plastic films

We have fabricated very flexible pentacene field-effect transistors with polyimide gate dielectric layers on plastic films with a mobility of 0.3cm2∕Vs and an on/off ratio of 105, and have measured their electrical properties under various compressive and tensile strains while changing the bending radius of the base plastic films systematically. We have found that the change in source-drain current with bending radius is reproducible and reversible when the bending radius is above 4.6mm, which corresponds to strains of ∼1.4±0.1%. Furthermore, the change in source-drain current does not depend on the direction of strain versus direction of current flow.