T. Maeda

Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs

This paper reviews the current critical issues regarding the device design of strained-Si MOSFETs and demonstrates that strained-Si-on-insulator (strained-SOI) structures can effectively solve these problems. The advantages, characteristics and challenges of strained-SOI CMOS technology are presented, on the basis of our recent results. Furthermore, a future possible direction of channel engineering using strained-Si/SiGe structures, into the deep sub-100 nm regime, is addressed.

Impact of Fermi level pinning inside conduction band on electron mobility of In x Ga 1−x As MOSFETs and mobility enhancement by pinning modulation

We clarified that Fermi levels at InGaAs MOS interfaces are pinned inside conduction band (CB) and that this pinning severely degrades the effective mobility. Also, the energy position of the Fermi level pinning (FLP) is found to be tunable. It is experimentally shown that the increase in the difference between the FLP position and the CB minimum (CBM) leads to high mobility at high Ns region. Also, possible physical origin for this FLP is proposed.

High velocity electron injection MOSFETs for ballistic transistors using SiGe/strained-Si heterojunction source structures

In this study, we have experimentally demonstrated, for the first time, the G/sub m/ enhancement due to higher velocity injection in a MOSFET structure with a source SiGe/strained-Si heterojunction (hetero-MOSFETs), compared to those in strained-SOIs (SSOI) and conventional SOIs. We present the concept and the simulated results of the hetero-source MOSFETs, followed by the process steps and experimental G/sub m/ characteristics.

Design for scaled thin film strained-SOI CMOS devices with higher carrier mobility

Physical mechanisms responsible for the reduction in both electron and hole mobility in thin strained-Si structures of strained-SOI CMOS devices are examined in detail. The slight decrease in electron mobility with thinning strained-Si layers is attributable to the quantum-mechanical confinement effect in strained-Si layers. Also, diffusion of Ge atoms into SiO/sub 2//strained Si interface is found to cause the generation of interface states near valence band edge, leading to the reduction in hole mobility in lower E/sub eff/ region through Coulomb scattering. Based on considerations of these factors affecting mobility, the strained-Si thickness and the Ge content are designed to realize high-speed strained-SOI CMOS under the 65 nm technology and beyond.

Demonstration of ultimate CMOS based on 3D stacked InGaAs-OI/SGOI wire channel MOSFETs with independent back gate

An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive back gate bias, VBG control.

Physical mechanism for high hole mobility in [110]-surface strained- and unstrained-MOSFETs

In this paper, in order to evaluate the higher hole mobility of the [110]-surface devices against that of the [100]-surface MOSFETs, we have studied the [110]-surface hole mobility behaviors of thin film (TF) strained-SOI, unstrained-SOI, and unstrained-bulk MOSFETs in detail, as functions of E/sub eff/, current flow direction, and temperature. We have introduced a model for [110]-surface hole mobility. We discuss the V/sub th/ control of the strained-SOIs by applying the back-gate bias under the buried oxide without controlling the channel dopant, as well as the transconductance enhancement down to the quarter-micron region. A device design concept for strained-CMOS is proposed to optimize the channel surface orientation and the drain current flow direction of n- and p-MOSFETs.

High mobility p-n junction-less InGaAs-OI tri-gate nMOSFETs with metal source/drain for ultra-low-power CMOS applications

We have successfully fabricated InGaAs-OI tri-gate nMOSFETs, for the first time. The devices were depletion-type (p-n junction-less) nFETs with Fin-channel width (W_fin) down to 20 nm and had metal source/drain structures. It was experimentally demonstrated that W_fin scaling effectively improved cut-off properties at N_d up to 5 × 10¹⁸ cm^-3 and the electron mobility in the narrowest channel (W_fin = 20 nm) was about 3x higher than that of the inversion layer. It was also demonstrated that enhancement of In content from 53% to 70% leaded to 30% I_on enhancement without I_off degradation.

Device characterizations and physical models of strained-Si channel CMOS

Recent progress on the development of strained-Si CMOS is reviewed with emphasis on the electrical properties. The device parameters extracted from strained-Si CMOS and the physical models, indispensable in describing the electrical characteristics, are presented. In addition, new requirements for device characterization, specific to strained-Si devices, which include V/sub th/ control and influence of Ge, are also addressed.

Ultra-thin strained-SOI CMOS for high temperature operation

We have investigated mobility behaviors of ultra-thin strained-Si channel in fully-depleted (FD) strained-SOI CMOS at high temperature, which is a realistic chip operation condition. Although the decrease in the mobility enhancement with a decrease in strained-Si thickness determines the lower limit of strained-Si thickness, we have found that this lower limit becomes thinner at temperatures higher than room temperature. This is because the mobility degradation by the quantum-mechanical confinement (QMC) effect and MOS interface charges is relaxed at higher temperatures. This fact means that strained-SOI CMOS with thinner strained Si films, advantageous in terms of short channel effects, is acceptable under the real operation conditions.

3D integration of high mobility InGaAs nFETs and Ge pFETs for ultra low power and high performance CMOS

InGaAs/Ge stacked 3D CMOS inverters have been successfully demonstrated down to Vdd = 0.2 V. The negligible degradation of the top and the bottom device characteristics indicates high technical feasibility of the InGaAs/Ge stacked 3D integration for ultra low-power and high performance CMOS.